CXD8900J (1/3)
il08d c-mos hips
?op view 40
41
42
43
44
1
2
3
4
5
6
v dd
gnd 28
27
26
25
24
23
22
21
20
19
18
v dd
gnd
gnd 39
38
37
36
35
34
33
32
31
30
29
v dd
gnd 7
8
9
10
11
12
13
14
15
16
17
v dd
gnd 1
2
3
4
5
6
7
8
9
10
11 i
i
i
i
? i
i
i
i
i
sadd
cs
ckd
ckx
gnd
rxclk
rxdata11
rxdata10
rxdata9
rxdata8
v dd 12
13
14
15
16
17
18
19
20
21
22 ? i
i
i
i
i
i
i
i
o
i gnd
rxdata7
rxdata6
rxdata5
rxdata4
rxdata3
rxdata2
rxdata1
rxdata0
po
reset 23
24
25
26
27
28
29
30
31
32
33 i
i
? ? o
o
o
o
o
o
o sync
clock
gnd
v dd
txdata0
txdata1
txdata2
txdata3
txdata4
txdata5
txdata6 34
35
36
37
38
39
40
41
42
43
44 ? ? o
o
o
o
o
o
? ? i gnd
v dd
txdata7
txdata8
txdata9
txdata10
txdata11
txclk
v dd
gnd
di pin
no. i/o signal pin
no. i/o signal pin
no. i/o signal pin
no. i/o signal
input
ckd
ckx
clock
cs
di
reset
rxclk
rxdata0
rxdata1
rxdata2
rxdata3
rxdata4
rxdata5
rxdata6
rxdata7
rxdata8
rxdata9
rxdata10
rxdata11
sadd
sync
output
txclk
txdata0
txdata1
txdata2
txdata3
txdata4
txdata5
txdata6
txdata7
txdata8
txdata9
txdata10
txdata11
po
: serial interface data clock
: register enable clock
: system clock
: chip select for serial interface, active low
: serial data input
: asynchronous reset, active low
: receive clock, 37.5 mhz
: data bit 0/cyclic pulse generator 1 load
: data bit 1/cyclic pulse generator 1 enable
: data bit 2
: data bit 3/cyclic pulse generator 2 load
: data bit 4/cyclic pulse generator 2 enable
: data bit 5
: data bit 6/cyclic pulse generator 3 load
: data bit 7/cyclic pulse generator 3 enable
: data bit 8
: data bit 9/cyclic pulse generator 4 load
: data bit 10/cyclic pulse generator 4 enable
: data bit 11
: serial address bus
: frame sync
: transmit clock, 37.5 mhz
: output data bit 0
: output data bit 1
: output data bit 2/cyclic pulse generator 1 pulse
: output data bit 3
: output data bit 4
: output data bit 5/cyclic pulse generator 2 pulse
: output data bit 6
: output data bit 7
: output data bit 8/cyclic pulse generator 3 pulse
: output data bit 9
: output data bit 10
: output data bit 11/cyclic pulse generator 4 pulse
: parametric output for test, not connected CXD8900J (2/3)
CXD8900J (3/3) reset 22 cs 2 di 44 sadd 1 ckd 3 ckx 4 serial
interface data
transfer delay
(cxd8054s) 4 x 12-bit
cyclic pulse
generators rxclk 6 sync 23 clock 24 rxdata0 -
rxdata11 20 - 13,
10 - 7 12 12 4 12 q d txclk 41 txdata0 -
txdata11 27 - 33,
36 - 40 12 12 5 + 1 12 12
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